Power- and thermal-aware testing of VLSI circuits and systems

With the increasing complexity of VLSI circuits and systems, their testing is becoming increasingly complex and time consuming. Apart from affecting the design turn-around time, it poses severe challenges to the test engineers in terms of meeting the power-budget and temperature limit of the chip. Power consumption during test is often much higher than in normal mode of operation. Increasing temperature during test affects quality of testing, with the possibility of good chips being declared as faulty and faulty ones passing the tests. As a result power-aware testing has drawn the attention of test engineers in the last decade. A good amount of power consumed during test is dissipated as heat, increasing temperature of it, which in turn, increases the leakage power consumption. This positive feedback may result in thermal run-away, leading to chip burn-out, in the extreme case. This tutorial attempts to provide an overview of contemporary techniques in power- and thermal-aware testing. Apart from discussing about the theoretical background, the tutorial will also demonstrate a number of tools and techniques developed by the research team over the last few years. It is expected that the attendees will learn about the algorithms behind such techniques, and will also get exposed to a number of tools integrating those algorithms.