A 50-GHz Phase-Locked Loop in 130-nm CMOS

Author

Cao, Changhua ; Ding, Yanping ; O, Kenneth K.

Author_Institution

Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL

fYear

2006

Firstpage

21

Lastpage

24

Abstract

A 50-GHz charge pump phase locked loop (PLL) utilizing an LC-oscillator based injection locked divider is fabricated in a 130-nm logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The circuit including buffers consumes 57 mW from 1.5/0.8 V supplies. The phase noise at 50 kHz, 1 MHz and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs -22-dBm second order harmonic frequencies between 91.8 and 101 GHz

Keywords

CMOS integrated circuits; buffer circuits; millimetre wave integrated circuits; nanotechnology; phase locked loops; phase noise; 0.8 V; 1 MHz; 1.5 V; 10 MHz; 130 nm; 45.9 to 50.5 GHz; 50 kHz; 57 mW; 91.8 to 101 GHz; LC-oscillator based injection locked divider; buffers; charge pump; logic CMOS process; phase noise; phase-locked loop; second order harmonic frequencies; CMOS logic circuits; CMOS process; CMOS technology; Frequency conversion; Inductors; Millimeter wave technology; Phase frequency detector; Phase locked loops; Power harmonic filters; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Conference_Location

San Jose, CA

Print_ISBN

1-4244-0075-9

Electronic_ISBN

1-4244-0076-7

Type

conf

DOI

10.1109/CICC.2006.320940

Filename

4114901