A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique

Author

Kanazawa, Yusuke ; Fujimoto, Yoshihisa ; Ré, Pascal Lo ; Miyamoto, Masayuki

Author_Institution

Adv. Technol. Res. Labs., Sharp Corp., Nara

fYear

2006

Firstpage

53

Lastpage

56

Abstract

A new ΔΣ ADC architecture using a triple sampling technique and a two-step summation scheme is presented. A 4th-order switched-capacitor ΔΣ ADC with a 4-bit quantizer is designed for a low-power direct-conversion digital TV receiver SoC. It achieves a 77.3-dB SNDR over a 4-MHz bandwidth with a 100-MHz clock frequency. The chip, fabricated in a 0.18-mum CMOS process, occupies 1.57 mm² and draws 15.3 mA from a 1.8-V supply. It achieves a 0.58-pJ/conversion FOM

Keywords

CMOS digital integrated circuits; delta-sigma modulation; low-power electronics; switched capacitor networks; 0.18 micron; 1.8 V; 100 MHz; 15.3 mA; 4 MHz; 4 bit; 4th-order switched-capacitor analog-to-digital converter; CMOS process; DeltaSigma analog-to-digital converter; low-power direct-conversion digital TV receiver; quantizer; system-on-chip; triple sampling technique; two-step summation scheme; Bandwidth; CMOS process; Circuits; Digital TV; Feedforward systems; Filtering; Filters; Frequency; Sampling methods; TV receivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Conference_Location

San Jose, CA

Print_ISBN

1-4244-0075-9

Electronic_ISBN

1-4244-0076-7

Type

conf

DOI

10.1109/CICC.2006.320962

Filename

4114907