A Useful Integration of Extra Nodes and the Leakage Current in Digital Circuits

VLSI circuit with higher performance and more functionality can cover wider cross-sections in applications. Designing such circuits requires additional peripherals and thus more nodes to be integrated with the mother circuit. Miniaturization of device channel length to sub-100nm dimension can allow high performance VLSI circuit design. However, such devices have a drawback of significantly higher leakage current. In VLSI circuit, an increase in number of node and leakage current leads to significant increase in its power dissipation. Over the past years, both at device, and circuit and system, level of design hierarchy, various guidelines have been proposed to address the issue. In this work, we have shown using simulations that despite the above facts, one can design economically ultra-low power digital circuits with extra nodes and such leakage current. CMOS inverter and SRAM cell while designed with our proposed technique results in 98.18% and 88.2 % reduction in static and writing power dissipation, respectively, as compared with their conventional design. The proposed technique also results in better noise margins in these circuits.