A Phase-Domain Continuous-Time 2nd-Order ΔΣ Frequency Digitizer

A frequency digitizer based on a continuous time delta-sigma PLL is presented. The architecture combines the demodulation and digitization process of a frequency modulated signal. This operation is done at a high IF frequency with an excellent accuracy thanks to the oversampling nature of the loop. Since the digitization occurs in phase domain, the power consumption of the digitizer drops significantly compared to the amplitude domain digitizers operating at the same frequency. In addition, owing to its high dynamic range, the digitizer can easily accommodate the frequency drift and DC offset that exist in the wireless environment. The design is implemented in a 0.18 μm CMOS technology. It operates at 128MHz carrier frequency and consumes 6.5 mW.