Pipelined maximal size matching scheduling algorithms for CIOQ switches

In this paper, we propose new pipelined request-grant-accept (RGA) and request-grant (RG) maximal size matching (MSM) algorithms to achieve speedup in combined input and output queueing (CIOQ) switches. To achieve a speedup factor S, in the proposed pipelined RGA/RG MSM algorithms, we pipeline operations of finding S matching in S scheduling cycles based on the observation that all matched inputs/outputs will not be used in later iterations in the same scheduling cycle. We show that our pipelined RGA/RG MSM algorithms reduce the scheduling time constraint by SI/(I+S-1), where I is the number of iterations allowed in each scheduling cycle. Taking the example of pipelined PIM, we evaluate the performance of the proposed algorithms by simulation. Simulation results have shown that pipelined PIM for CIOQ switches with speedup of 2 under both Bernoulli and bursty arrivals.