Evaluation of switch schedulers for embedded systems

We evaluate hardware and software implementations of a centralized and a distributed scheduler for embedded packet switches. The evaluation is performed for embedded system implementation, on a system that includes an FPGA and an embedded, on-chip processor. The results demonstrate that, in contrast to expectations, centralized schedulers provide better performance than distributed ones in hardware implementations. In software implementations for embedded processors, surprisingly, distributed schedulers achieve better performance, due to better management of the processor´s limited resources and simpler code.