Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-A

In this paper, we present the concurrent design method of delta-sigma modulator by using analog HDL. In our method, a few blocks are modeled at transistor level and the other blocks are done at behavioral level. For every block, similar modeling is done, and the simulations are performed at the transistor and behavioral mixed level. As a result, specification of every block is derived without the enormous costs so that the whole circuit is simulated repeatedly. We show our method is useful and efficient for the analog circuit design by designing the first-order delta-sigma modulator