DocumentCode
1679380
Title
Low Cost Test of High Bandwidth Embedded Memories
Author
Gorman, Kevin W. ; Anand, Darren ; Pomichter, Gary ; Corbin, William R.
Author_Institution
IBM Syst. & Technol. Group, Essex Junction, VT
fYear
2006
Firstpage
445
Lastpage
448
Abstract
This work presents architectures and methods necessary for providing efficient and thorough test of high bandwidth embedded memories using low speed ATE. Details are also provided on the techniques used to minimize test related silicon area and test time requirements. This combination of flexible at-speed test with minimal circuitry and ATE requirements, and reduced time under test, leads to lower cost production of embedded memories
Keywords
DRAM chips; automatic test equipment; built-in self test; embedded systems; DRAM chips; automatic test equipment; built-in self test; embedded memories; Bandwidth; Built-in self-test; Circuit testing; Clocks; Costs; Logic testing; Random access memory; Silicon; System testing; Tiles;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location
San Jose, CA
Print_ISBN
1-4244-0075-9
Electronic_ISBN
1-4244-0076-7
Type
conf
DOI
10.1109/CICC.2006.320820
Filename
4114998
Link To Document