A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters

Author

Ueno, Takeshi ; Ito, Tomohiko ; Kurose, Daisuke ; Yamaji, Takafumi ; Itakura, Tetsuro

Author_Institution

Corporate R&D Center, Toshiba Corp., Kawasaki

fYear

2006

Firstpage

501

Lastpage

504

Abstract

This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, the authors employed the I/Q amplifier sharing technique (Kurose, et al., 2005) in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively

Keywords

CMOS integrated circuits; analogue-digital conversion; differential amplifiers; operational amplifiers; pipeline processing; 1.2 V; 10 bit; 90 nm; CMOS technology; analog-digital converters; common-mode disturbances; common-source amplifiers; operational amplifiers; pseudo-differential amplifiers; wireless communication; Bandwidth; Breakdown voltage; CMOS technology; Differential amplifiers; Digital circuits; Energy consumption; Indium tin oxide; Power amplifiers; Power supplies; Research and development;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Conference_Location

San Jose, CA

Print_ISBN

1-4244-0075-9

Electronic_ISBN

1-4244-0076-7

Type

conf

DOI

10.1109/CICC.2006.320893

Filename

4115010