• DocumentCode
    1679693
  • Title

    Low-Power Design of Pipeline A/D Converters

  • Author

    Kawahito, S.

  • Author_Institution
    Res. Inst. of Electron., Shizuoka Univ., Hamamatsu
  • fYear
    2006
  • Firstpage
    505
  • Lastpage
    512
  • Abstract
    In this paper, low-power design techniques of highspeed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A power optimization of pipeline and parallel pipeline ADCs based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC is also presented. Finally, the theoretical minimum of required power in pipeline ADCs is discussed
  • Keywords
    analogue-digital conversion; integrated circuit design; low-power electronics; parallel architectures; pipeline processing; analog-digital converters; parallel-pipeline architectures; power optimization; response time; Analog circuits; Circuits and systems; Delay; Design optimization; Digital circuits; Pipeline processing; Power dissipation; Power system modeling; Sampling methods; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    1-4244-0075-9
  • Electronic_ISBN
    1-4244-0076-7
  • Type

    conf

  • DOI
    10.1109/CICC.2006.320894
  • Filename
    4115011