DocumentCode
1680853
Title
Fault tolerant practices on network processors for dependable network processing
Author
Luo, Yan ; Fan, Jie
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Lowell, MA
fYear
2008
Firstpage
1
Lastpage
7
Abstract
In this paper, we study how to provide dependable network processing through multi-core based network processors (NPs). We present the performance analysis results of an NP based network system and motivate our research. We propose to use the redundant cores available in an NP to handle faults. We outline a fault-tolerant (FT) task model specifically for NP based applications and describe our implementation taking advantage of hardware features of an Intel IXP2xxx NP. A set of experiments are conducted to evaluate the performance and effectiveness of a FT-enabled NP system. The experiment results show that our fault- tolerant design can effectively improve the schedulability of the system.
Keywords
fault tolerant computing; microprocessor chips; multiprocessing systems; performance evaluation; processor scheduling; dependable network processing; fault handling; fault tolerance; multicore based network processors; performance analysis; redundant cores; system schedulability; task model; Complex networks; Coprocessors; Fault tolerance; Fault tolerant systems; Hardware; Performance analysis; Processor scheduling; Random access memory; Redundancy; SDRAM;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on
Conference_Location
Miami, FL
ISSN
1530-2075
Print_ISBN
978-1-4244-1693-6
Electronic_ISBN
1530-2075
Type
conf
DOI
10.1109/IPDPS.2008.4536150
Filename
4536150
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