DocumentCode
1681690
Title
A Unity-Gain Buffer with Reduced Offset and Gain Error
Author
Xing, Guangmao ; Lewis, Stephen H. ; Viswanathan, T.R.
Author_Institution
Marvell Semicond., Santa Clara, CA
fYear
2006
Firstpage
825
Lastpage
828
Abstract
A unity-gain buffer has been fabricated in 0.35-mum CMOS technology. The circuit uses feed forward and local feedback in a cascaded source follower circuit as well as two global feedback loops: one to reduce the output resistance, gain error, and offset and a second loop to further reduce gain error. The buffer consumes 3.7 mW at 3.3 V and has a bandwidth of 92 MHz when driving a 13-pF capacitive load
Keywords
CMOS integrated circuits; buffer circuits; feedback amplifiers; operational amplifiers; 0.35 micron; 13 pF; 3.3 V; 3.7 mW; 92 MHz; CMOS technology; cascaded source follower circuit; gain error; global feedback loops; reduced offset; unity-gain buffer; Bandwidth; CMOS technology; Feedback amplifiers; Feedback circuits; Feedback loop; Feeds; Linearity; MOSFETs; Output feedback; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Conference_Location
San Jose, CA
Print_ISBN
1-4244-0075-9
Electronic_ISBN
1-4244-0076-7
Type
conf
DOI
10.1109/CICC.2006.320831
Filename
4115080
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