Delay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform

Delay variability due to dynamic power supply noise is elucidated by on-chip signal waveform measurements at 100-ps/100-muV resolutions applied to a 180-nm CMOS digital circuit. A single-tone noise model represents a dynamic power supply noise waveform with the most significant frequency component and leads to circuit-level simulation that can efficiently capture the effects of switching signal waveform modulation on delay in a logic gate. Simulation and measurements show excellent agreement in delay variation, even with relative differences among clock domains in timing as well as in noise strength. The proposed delay simulation technique actualizes the delay analysis in consideration of dynamic power supply noise and thus consolidates the timing closure especially in a high speed digital design