System-level routing of mixed-signal ASICs in WREN

Techniques for global and detailed routing of the macrocell-style analog core of a mixed-signal ASIC are discussed. A comparatively simple geometric model of the problem is combined with an aggressive simulated annealing formulation that selects paths while accommodating numerous signal-integrity constraints. Experimental results demonstrate that it is critical to attack such constraints both globally (system-level) and locally (channel-level) to meet designer-specified performance targets.<>