A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup

Author

Hanzawa, Satoru ; Sakata, Takeshi ; Kajigaya, Kazuhiko ; Takemura, Riichiro ; Sekiguchi, Tomonori ; Kawahara, Takayuki

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

Volume

2

fYear

2005

Firstpage

1048

Abstract

A new ternary/quaternary content-addressable memory (CAM) architecture using a one-hot-spot block code and two new schemes - for large-scale flow-table lookup has been developed. An NPU-side IP-address compression scheme enables a network processor unit (NPU) to track a CAM and its usage so that IP addresses can be efficiently stored with one-hot-spot block code. A dynamic re-configurable CODEC scheme enables the CAM to store both ternary and quaternary data. With 72-bit data width per word, this CAM, using 0.13-μm stand-alone DRAM technology, can achieve 1.5 million entries, namely, six times more than a conventional static ternary CAM.

Keywords

block codes; data compression; memory architecture; table lookup; 0.13 mum; NPU-side IP-address compression scheme; dynamic reconfigurable CODEC scheme; large-scale flow-table lookup; network processor unit; one-hot-spot block code; quaternary CAM architecture; stand-alone DRAM technology; ternary CAM architecture; Associative memory; Block codes; CADCAM; Codecs; Computer aided manufacturing; Electronic mail; Laboratories; Large-scale systems; Quality of service; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, 2005. ICC 2005. 2005 IEEE International Conference on

Print_ISBN

0-7803-8938-7

Type

conf

DOI

10.1109/ICC.2005.1494508

Filename

1494508