A logic simulation engine based on a modified data flow architecture

An optimum application-specific data flow architecture for accelerating the standard event driven logic simulation is developed. A conservative distributed simulation algorithm which minimizes the use of NULL messages is also developed, along with a pseudodynamic data flow architecture to implement this distributed algorithm efficiently. A comparison of the standard event driven algorithm-based data flow accelerator to the distributed simulation algorithm-based accelerator is made on several benchmark circuits. The distributed simulation algorithm on the specialized data flow accelerator outperforms the standard event driven algorithm based data flow accelerator by a factor of three in most cases.<>