Portable parallel test generation for sequential circuits

Author

Ramkumar, B. ; Banerjee, P.

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

fYear

1992

Firstpage

220

Lastpage

223

Abstract

A parallel test generation algorithm, ProperTEST, for sequential circuits that is portable across a range of MIMD parallel architectures is discussed. It uses prioritized execution to ensure consistent speedups as the number of processors is increased. This consistency is achieved without loss of fault coverage with increase in the number of processors. This also permits the use of parallel processing to improve the fault coverage when the execution time is bounded. Results on ISCAS 89 benchmark programs are provided on a shared memory machine, a message passing machine, and a network of workstations. ProperTEST was run unchanged on these different architectures.<>

Keywords

automatic testing; integrated circuit testing; logic testing; parallel architectures; sequential circuits; ISCAS 89 benchmark programs; MIMD parallel architectures; ProperTEST; fault coverage; message passing machine; portable parallel test generation; prioritized execution; sequential circuits; shared memory machine; Automatic testing; Integrated circuit testing; Logic circuit testing; Parallel architectures; Sequential logic circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-3010-8

Type

conf

DOI

10.1109/ICCAD.1992.279371

Filename

279371