Delay and bus current evaluation in CMOS logic circuits

Author

Nabavi-Lishi, A. ; Rumin, N.

Author_Institution

Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada

fYear

1992

Firstpage

198

Lastpage

203

Abstract

An accurate and fast analytical technique for computing the delay and the maximum supply current in a CMOS inverter is presented. It accounts for the effects of input slope, output load, transistor size, and short-circuit current. The accuracy is within 10% of the HSPICE level-3 model and the speed is more than three orders of magnitude faster than HSPICE. An extension of this technique is shown for the calculation of the delay and the maximum supply current of a chain of inverters, without recourse to integration. An efficient method for computing the total current waveform of the chain is also presented. The relative speed of computing the current waveform exceeds two orders of magnitude compared to HSPICE.<>

Keywords

CMOS integrated circuits; delays; invertors; logic CAD; logic circuits; CMOS logic circuits; HSPICE level-3 model; bus current evaluation; delay; input slope; inverter; maximum supply current; output load; short-circuit current; total current waveform; transistor size; CMOS integrated circuits; Delay effects; Design automation; Inverters; Logic circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-3010-8

Type

conf

DOI

10.1109/ICCAD.1992.279375

Filename

279375