Rule-based routing in massively parallel systems

In order to increase the performance of an interconnection network, efficient routing schemes are required which adapt to the system state. In this paper an approach to routing hardware is introduced which allows to tailor it flexibly to different routing algorithms and to incorporate different kinds of information easily within a routing decision. The key concept is to use a rule-based specification to represent the routing algorithm which is executed by a fixed rule-interpreter with an interchangeable rule-base. This allows to provide an universal routing chip with a highly flexible and efficient hardware implementation even of sophisticated routing algorithms. Three different examples illustrate the application of such a rule-based router. The discussion of implementation issues shows that a rule-based router is well suited for an implementation with state-of-the-art VLSI-technologies, e.g. a single-chip ASIC