An algorithm to reduce test application time in full scan designs

Author

Lee, S.Y. ; Saluja, K.K.

Author_Institution

Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA

fYear

1992

Firstpage

17

Lastpage

20

Abstract

An algorithm for generating a test with fewer test clocks for full scan designs by using combinational and sequential test generation algorithms adaptively is presented. Heuristics combining tests measures and scan strategies are introduced. The algorithm, ´Test Application time Reduction for Full scan designs´ (TARF), is implemented and tested on a set of ISCAS sequential benchmark circuits. The results show that TARF achieves the same test coverage as combinational test generators but with fewer test clocks.<>

Keywords

design for testability; integrated circuit testing; logic CAD; logic testing; sequential circuits; ISCAS sequential benchmark circuits; TARF; combinational test generation algorithms; design for testability; full scan designs; heuristics; scan strategies; sequential test generation algorithms; test application time; test clocks; test coverage; tests measures; Design automation; Design for testability; Integrated circuit testing; Logic circuit testing; Sequential logic circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-3010-8

Type

conf

DOI

10.1109/ICCAD.1992.279405

Filename

279405