A novel asynchronous ALU for massively parallel architectures

A self-timed asynchronous bit serial massively parallel architecture is currently being developed to overcome limitations associated with clocked control, namely those of fixed word length, causing performance loss for small magnitude data, clock skew and scalability. The paper introduces the self-timed communication techniques and arithmetic logic unit (ALU) of the adopted research vehicle, the self-timed single instruction systolic array (ST-SISA), highlighting the novel architectures developed for variable length bit serial logical and arithmetic operations. Two self-timed delay insensitive techniques have been used to produce both a 2 phase (return to zero) and a 4 phase (non-return to zero) ALU for means of comparison. The self-timed designs and communication techniques developed are evaluated on a cost and performance basis demonstrating the speed up potential of the novel self-timed approach