Parallel graph reduction with the PACE architecture

Author

Waite, M.E. ; Reynolds, T.J. ; Ieromnimon, F.Z.

Author_Institution

Dept. of Comput. Sci., Essex Univ., Colchester, UK

fYear

1996

Firstpage

448

Lastpage

454

Abstract

The PACE architecture is an extensible, distributed memory multiprocessor that is designed specifically to support the graph reduction model of computation. PACE differs from most other research projects in this area in that it advocates the use of a specially designed processor, rather than currently available devices, as the basic replicable node. We present the design of a prototype version of the new processor, together with the latest results obtained by simulating the parallel execution of example programs on both a detailed Verilog description of the hardware and a much faster C simulator (arrays of up to 200 processors are simulated)

Keywords

distributed memory systems; graph theory; parallel architectures; parallel programming; virtual machines; C simulator; PACE architecture; Verilog description; basic replicable node; distributed memory multiprocessor; graph reduction model; parallel execution; parallel graph reduction; prototype version; Computational modeling; Computer architecture; Computer science; Context; Distributed computing; Finishing; Hardware design languages; Parallel processing; Process design; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Processing, 1996. PDP '96. Proceedings of the Fourth Euromicro Workshop on

Conference_Location

Braga

Print_ISBN

0-8186-7376-1

Type

conf

DOI

10.1109/EMPDP.1996.500618

Filename

500618