A PGAS Execution Model for Efficient Stencil Computation on Many-Core Processors

Author

Ikei, Mitsuru ; Sato, Mitsuhisa

Author_Institution

Intel Archit. Technol. Group, Intel K.K., Tokyo, Japan

fYear

2014

fDate

26-29 May 2014

Firstpage

305

Lastpage

314

Abstract

A efficient PGAS execution model on many-core processor for stencil computation is proposed and implemented. We use XcalableMP as a base language and we modify its runtime well fit in many-core processors. The runtime uses processes for parallel execution and global arrays of the stencil codes are broken into blocked sub-arrays placed on shared memory. Using two stencil codes, Laplace and Himeno, we evaluated its performance. In the evaluation, we show (1) Blocking improves locality of memory access during computation therefore improves total CPU execution time. (2) Direct data access using shared memory can relieve communication burden of sub-array halo exchanges.

Keywords

parallel processing; shared memory systems; PGAS execution model; XcalableMP; base language; blocked subarrays; direct data access; global arrays; many-core processor; memory access locality; parallel execution; shared memory; stencil codes; stencil computation; subarray halo exchanges; total CPU execution time; Arrays; Electronics packaging; Instruction sets; Programming; Runtime; PGAS; many integrated core; parallel; stencil code;

fLanguage

English

Publisher

ieee

Conference_Titel

Cluster, Cloud and Grid Computing (CCGrid), 2014 14th IEEE/ACM International Symposium on

Conference_Location

Chicago, IL

Type

conf

DOI

10.1109/CCGrid.2014.20

Filename

6846466