A scalable decoder architecture for linear congruential LDPC codes

Maximal length linear congruential sequence (MLLCS) based LDPC codes have the advantage that the LDPC code graph can be generated at the receiver without having to explicity store the graph. Hence, these codes are advantageous when the same hardware needs to be used for different sets of rates and lengths. In this paper, we reveal an inherent structure in these codes that facilitates parallel implementation of the decoding algorithm. Based on this, we present an architecture for the MLLCS-LDPC decoder that facilitates parallel scalable implementation and joint code-decoder design.