DocumentCode
1688515
Title
A test method for delay faults in NoC interconnects
Author
He Cheng ; Shu Yan Jiang ; Yue Liu ; Shan Shan Jiang ; Li Chen
Author_Institution
Sch. of Autom. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear
2013
Firstpage
371
Lastpage
374
Abstract
Network-on-Chip (NoC) delay faults can only be detected when NoC works at normal operating speed, so it is very hard to test such faults. In this paper, we propose a method for at-speed testing of delay faults in NoC interconnects. Based on the NoC delay fault model, we first formulate the problems of the NoC delay faults. Then, we propose a delay test method for NoC data transfer through handshaking and add an extra hardware respectively on the transmitter and the receiver as test circuits, achieving the automatic testing of the delay faults. Finally, the analysis shows that the proposed method guarantees that all the good chips will not be detected as faulty, avoiding the waste of chip resources.
Keywords
integrated circuit interconnections; integrated circuit testing; network-on-chip; NoC data transfer; NoC delay fault model; NoC interconnects; delay fault automatic testing; delay fault test method; network-on-chip delay faults; Circuit faults; Clocks; Delays; Integrated circuit interconnections; Receivers; Testing; Transmitters; delay faults; interconnects; network-on-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Applied Superconductivity and Electromagnetic Devices (ASEMD), 2013 IEEE International Conference on
Conference_Location
Beijing
Print_ISBN
978-1-4799-0068-8
Type
conf
DOI
10.1109/ASEMD.2013.6780797
Filename
6780797
Link To Document