A New SRAM Cell Design for Both Power and Performance Efficiency

This paper presents a new six-transistor static random access memory (6 T SRAM) cell with significantly reduced power consumption that achieves high read and write performance. Unlike traditional 6 T SRAMs, this study proposes an asymmetric 6 T SRAM which uses a single line to implement read or write operations without reducing performance. This design not only reduces power consumption, but also improves read and write performance. The proposed SRAM design is implemented with UMC 90 nm, 1.0-V supply voltage CMOS technologies. Compared to conventional six transistor SRAM cells, the new cell design successfully power consumption by 40-60%. In addition, the read and write performance has been improved by 13.6% and 41.2%.