DocumentCode
1690254
Title
Reusable context pipelining for low power coarse-grained reconfigurable architecture
Author
Kim, Yoonjin ; Mahapatra, Rabi N.
Author_Institution
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX
fYear
2008
Firstpage
1
Lastpage
8
Abstract
Coarse-grained reconfigurable architectures (CGRA) require many processing elements and a configuration memory unit (configuration cache) for reconfiguration of the ALU array elements. This structure consumes significant amount of power. Power reduction during reconfiguration is necessary for the reconfigurable architecture to be used as a competitive IP core in embedded systems. In this paper, we propose a power-conscious reusable context pipelining architecture for CGRA that efficiently reduces power consumption in configuration cache without performance degradation. Experimental results show that the proposed approach saves up to 57.97% of the total power consumed in the configuration cache with reduced configuration cache size compared to the previous approach.
Keywords
pipeline processing; reconfigurable architectures; embedded systems; low power coarse-grained reconfigurable architecture; power consumption; reusable context pipelining; Application software; Application specific integrated circuits; Computational modeling; Computer architecture; Embedded system; Energy consumption; Hardware; Pipeline processing; Power system reliability; Reconfigurable architectures;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on
Conference_Location
Miami, FL
ISSN
1530-2075
Print_ISBN
978-1-4244-1693-6
Electronic_ISBN
1530-2075
Type
conf
DOI
10.1109/IPDPS.2008.4536523
Filename
4536523
Link To Document