• DocumentCode
    1692545
  • Title

    Processor allocation algorithm based on Frame Combing with Memorization for 2D mesh CMPs

  • Author

    Daoud, Luka B. ; Ragab, M.E. ; Goulart, Victor

  • Author_Institution
    ECE Dept., Egypt-Japan Univ. of Sci. & Technol. (E-JUST), Egypt
  • fYear
    2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Processor Allocator (PA) is one of the main components to achieve high performance Chip Multiprocessors (CMPs). The task of the PA is to assign a set of processors to execute an incoming job scheduled by the Operating System (OS). An efficient PA is one that allocates an incoming job, if a suitable free submesh exists, with minimum overhead. In this paper, we propose a new contiguous processor allocation algorithm, Frame Combing with Memorization (FCM) for 2D mesh CMPs, which is fast, has complete submesh recognition, and assigns a set of processors without creating coverage areas for the incoming job. Our proposed algorithm outperforms other existing allocation strategies based on busy array approach such as Improved First Fit (IFF), and Better First Fit (BFF), or even Right of Busy Submeshes (RBS), a fast busy list based PA algorithm. Performance evaluation has been done with different job sets over different network sizes and at different network occupations. Our proposed PA is in average 3 up to 5 times faster than IFF, BFF and RBS for allocating small job (size 4×2) in a network size 10×10. For big network sizes (30×30), it is up to 60, 79, and 48 times faster than IFF, BFF, and RBS, respectively.
  • Keywords
    microprocessor chips; multiprocessing systems; network-on-chip; operating systems (computers); 2D mesh chip multiprocessors; better first fit; frame combing with memorization; improved first fit; operating system; processor allocation algorithm; right of busy submeshes; submesh recognition; Algorithm design and analysis; Arrays; Computers; Mesh networks; Operating systems; Out of order; Resource management; Frame Combing with Memorization (FCM); NoC (Network-on-Chip); chip multiprocessors; contiguous processor allocation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (LASCAS), 2012 IEEE Third Latin American Symposium on
  • Conference_Location
    Playa del Carmen
  • Print_ISBN
    978-1-4673-1207-3
  • Type

    conf

  • DOI
    10.1109/LASCAS.2012.6180351
  • Filename
    6180351