Extracting CAD models for quantifying noise coupling between vias in PCB layouts

Author

Luan, S. ; Fan, J. ; Liu, W. ; Xiao, F. ; Knighten, J. ; Smith, N. ; Alexander, R. ; Nadolny, J. ; Kami, Y. ; Drewniak, J.

Author_Institution

Missouri Univ., Rolla, MO, USA

fYear

2002

fDate

6/24/1905 12:00:00 AM

Firstpage

343

Lastpage

346

Abstract

A method to extract a lumped element prototype SPICE model is used to study noise coupling between non-parallel traces on a PCB. The parameters in this model are extracted using a PEEC-like approach, a Circuit Extraction approach based on a Mixed-Potential Integral Equation formulation (CEMPIE). Without large numbers of unknowns, the SPICE model saves computation time. Also, it is easy to incorporate into system SPICE net list to acquire the system simulation result considering the coupling between traces on the printed circuit board (PCB). A representative case is studied, and the comparison of measurements, CEMPIE simulation, and SPICE modeling are given.

Keywords

SPICE; circuit layout CAD; circuit noise; equivalent circuits; integral equations; printed circuit layout; CAD model; CEMPIE simulation; PCB layout; PEEC; circuit extraction; lumped element SPICE model; mixed-potential integral equation; noise coupling; nonparallel traces; parameter extraction; via; Circuit noise; Computational modeling; Coupling circuits; Crosstalk; Distributed parameter circuits; Integral equations; Power transmission lines; Prototypes; SPICE; Transmission line theory;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2002. Proceedings. 52nd

ISSN

0569-5503

Print_ISBN

0-7803-7430-4

Type

conf

DOI

10.1109/ECTC.2002.1008118

Filename

1008118