DocumentCode
1694761
Title
SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator
Author
Ozaki, Nobuaki ; Amano, Hideharu ; Nakamura, Hiroshi ; Usami, Kimiyoshi ; Namiki, Mitaro ; Kondo, Masaaki
Author_Institution
Amano Lab., Keio Univ., Yokohama, Japan
fYear
2011
Firstpage
1
Lastpage
3
Abstract
SLD(Silent Large Datapath)-1 is a prototype accelerator for media processing consisting of a large Processing Element (PE) array which includes 24bit 8 × 8 PEs with combinatorial circuits and a small micro-controller for data memory access. It was fabricated in 2.1mm × 4.2mm 65 nm CMOS, and achieves 1.356GOPS/11mW sustained performance by reducing overhead of clock tree and the benefit of voltage scaling.
Keywords
CMOS integrated circuits; combinational circuits; low-power electronics; CMOS; SLD-1; clock tree overhead; combinatorial circuits; data memory access; media processing; power 11 mW; processing element array; silent large datapath; size 65 nm; ultralow power reconfigurable accelerator; voltage scaling; word length 24 bit; Arrays; Clocks; Delay; Prototypes; Random access memory; Registers; Superluminescent diodes; 65nmCMOS; Low Power; Reconfigurable System;
fLanguage
English
Publisher
ieee
Conference_Titel
Cool Chips XIV, 2011 IEEE
Conference_Location
Yokohama
Print_ISBN
978-1-61284-883-9
Electronic_ISBN
978-1-61284-882-2
Type
conf
DOI
10.1109/COOLCHIPS.2011.5890918
Filename
5890918
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