Technology exploration for adaptive power and frequency scaling in 90nm CMOS

Author

Meijer, Maurice ; Pessolano, Francesco ; De Gyvez, José Pineda

Author_Institution

Philips Res. Labs., Eindhoven, Netherlands

fYear

2004

Firstpage

14

Lastpage

19

Abstract

In this paper we examine the expectations and limitations of design technologies such as adaptive voltage scaling (AVS) and adaptive body biasing (ABB) in a modem deep sub-micron process. To serve this purpose, a set of ring oscillators was fabricated in a 90nm triple-well CMOS technology. The analysis hereby presented is based on two ring oscillators running at 822MHz and 93MHz, respectively. Measurement results indicate that it is possible to reach 13.8× power savings by 3.4× frequency downscaling using AVS, ±11% power and ±8% frequency tuning at nominal conditions using ABB only, 22× power savings with 5× frequency downscaling by combining AVS and ABB, as well as 22× leakage reduction.

Keywords

CMOS integrated circuits; UHF oscillators; VHF oscillators; integrated circuit design; leakage currents; low-power electronics; nanoelectronics; voltage-controlled oscillators; 822 MHz; 90 nm; 93 MHz; adaptive body biasing; adaptive frequency scaling; adaptive power scaling; adaptive voltage scaling; deep submicron process; design technology exploration; frequency downscaling; leakage reduction; performance compensation; performance optimization; power savings; ring oscillators; triple-well CMOS technology; CMOS technology; Energy consumption; Frequency measurement; Modems; Power measurement; Power supplies; Ring oscillators; Tuning; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on

Print_ISBN

1-58113-929-2

Type

conf

DOI

10.1109/LPE.2004.1349300

Filename

1349300