DocumentCode
1697375
Title
Structure and metrology for a single-wire analog testability bus
Author
Lu, Yunsheng ; Mao, Weiwei ; Dandapani, R. ; Gulati, Ravi K.
Author_Institution
Dept. of Electr. & Comput. Eng., Colorado Univ., Colorado Springs, CO, USA
fYear
34608
Firstpage
919
Lastpage
928
Abstract
A structure for testing the interconnect faults and measurement of discrete components on mixed-signal boards is proposed. The structure requires one analog pin in addition to the IEEE 1149.1 pins on each mixed-signal IC. Simulation results are provided to show the accuracy of the metrology
Keywords
IEEE standards; automatic testing; boundary scan testing; design for testability; fault location; mixed analogue-digital integrated circuits; printed circuit testing; IEEE 1149.1 pins; analog pin; discrete components; interconnect faults; mixed-signal IC; mixed-signal boards; simulation results; single-wire analog testability bus; Analog integrated circuits; Current measurement; Integrated circuit interconnections; Metrology; Pins; Switches; Switching circuits; Testing; Voltage; Voltmeters;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1994. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-2103-0
Type
conf
DOI
10.1109/TEST.1994.528041
Filename
528041
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