A 13 ns Mb CMOS EPROM using 1-T FAMOS technology

Author

Rosendale, G. ; Payne, J. ; Pathak, S. ; Randazzo, T. ; Larsen, B. ; Erickson, D. ; Allum, D. ; Blaha, F.

Author_Institution

Atmel Corp., San Jose, CA, USA

fYear

1993

Firstpage

42

Lastpage

43

Abstract

A 128-kB*8-b EPROM (electrically programmable read-only memory) with a 1-T FAMOS cell is described which demonstrates a 13-ns address access time, allowing the elimination of shadow SRAM (static random-access memory) in high-speed embedded-control and DSP applications. Access time is achieved through a combination of technology and architectural features, without differential sensing or address transition detection. The EPROM is fabricated in double-layer-metal 0.8- mu m CMOS for low cost and compactness. A split-plane, rotated architecture using second-layer metal for wordline strapping allows the columns to be kept relatively short and minimizes wordline RC delay.<>

Keywords

CMOS integrated circuits; EPROM; integrated memory circuits; 0.8 micron; 1-T FAMOS cell; 1024000 bit; 128 kbyte; 13 ns; CMOS EPROM; DSP applications; FAMOS technology; double-layer-metal; electrically programmable; high-speed embedded-control; read-only memory; split-plane rotated architecture; wordline strapping; CMOS technology; Circuits; Decoding; Delay; EPROM; Latches; Nonvolatile memory; Paper technology; Pulse amplifiers; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0987-1

Type

conf

DOI

10.1109/ISSCC.1993.280092

Filename

280092