DocumentCode
1699421
Title
An on-chip all-digital measurement circuit to characterize phase-locked loop response in 45-nm SOI
Author
Fischette, Dennis ; DeSantis, Richard ; Lee, John Haeseon
Author_Institution
Adv. Micro Devices, Inc., Sunnyvale, CA, USA
fYear
2009
Firstpage
609
Lastpage
612
Abstract
An all-digital measurement circuit, built in 45-nm SOI-CMOS, enables on-chip characterization of phase-locked loop (PLL) response to a self-induced phase step. This technique allows estimation of PLL closed-loop bandwidth and jitter peaking. The circuit can be used to plot step-response vs. time, measure static phase error, and observe phase-lock status.
Keywords
CMOS integrated circuits; phase locked loops; jitter peaking; phase-locked loop response; static phase error; Bandwidth; Circuits; Clocks; Detectors; Frequency; Jitter; Phase detection; Phase locked loops; Phase measurement; Transfer functions;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-4071-9
Electronic_ISBN
978-1-4244-4073-3
Type
conf
DOI
10.1109/CICC.2009.5280739
Filename
5280739
Link To Document