A 10-bit 210MHz CMOS D/A Converter for WLAN

This paper describes a 10-bit 210MHz CMOS current-mode Digital to Analog Convener (DAC) consisting of 6 bit MSB current cell matrix Sub-DAC, 2 bit mSB unary current source Sub-DAC, and 2 bit LSB binary weighting Sub-DAC for Wireless LAN application. A new deglitch circuit is proposed to control a crossing point of signals and minimize a glitch energy. The proposed 10-bit CMOS current mode DAC was designed by a 0.35 μm CMOS double-poly four-metal technology. The effective chip area is 5mm². The chip measurement results show a converter rate of 210MHz, DNL/INL of ±0.7LSB/±1.1LSB, a glitch energy of 76pV·sec, a SNR of 50dB, a SFDR of 53dB at 200MHz sampling clock and a power dissipation of 83mW at 3.3V.