DocumentCode
170114
Title
Diagnosis of multiple faults with highly compacted test responses
Author
Cook, Alan ; Wunderlich, H.-J.
Author_Institution
Inst. of Comput. Archit. & Comput. Eng., Univ. of Stuttgart, Stuttgart, Germany
fYear
2014
fDate
26-30 May 2014
Firstpage
1
Lastpage
6
Abstract
Defects cluster, and the probability of a multiple fault is significantly higher than just the product of the single fault probabilities. While this observation is beneficial for high yield, it complicates fault diagnosis. Multiple faults will occur especially often during process learning, yield ramp-up and field return analysis. In this paper, a logic diagnosis algorithm is presented which is robust against multiple faults and which is able to diagnose multiple faults with high accuracy even on compressed test responses as they are produced in embedded test and built-in self-test. The developed solution takes advantage of the linear properties of a MISR compactor to identify a set of faults likely to produce the observed faulty signatures. Experimental results show an improvement in accuracy of up to 22 % over traditional logic diagnosis solutions suitable for comparable compaction ratios.
Keywords
built-in self test; fault diagnosis; integrated circuit testing; integrated circuit yield; probability; MISR compactor; built-in self-test; compacted test responses; compressed test responses; defects cluster; embedded test; faulty signatures; field return analysis; linear properties; logic diagnosis; multiple fault diagnosis; multiple fault probability; process learning; yield ramp-up; Accuracy; Built-in self-test; Circuit faults; Compaction; Equations; Fault diagnosis; Mathematical model; Diagnosis; Multiple Faults; Response Compaction;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium (ETS), 2014 19th IEEE European
Conference_Location
Paderborn
Type
conf
DOI
10.1109/ETS.2014.6847796
Filename
6847796
Link To Document