DocumentCode
1701468
Title
RZ/NRZ dual-rail decoding scheme to reduce switching activities in asynchronous circuits
Author
Lee, Won-Chul ; Lee, Je-Hoon ; Cho, AndKyoung-Rok
Author_Institution
Commun. Circuits & Syst. Design Lab., Chung-Buk Nat. Univ., Cheongju, South Korea
fYear
2004
Firstpage
266
Lastpage
269
Abstract
In this paper, we present a new mixture RZ/NRZ dual-rail transmission method to reduce the power consumption associated with data switching and to overcome the zero switching overhead of the RZ dual-rail decoding scheme. The dual-rail data encoding is useful to detect the completion signal of each module in the asynchronous circuits using the DI delay model. However, the dual-rail scheme gives some disadvantages, large chip area and higher power consumption than single-rail counterparts. The proposed method reduces the switching activities of the circuit significantly introducing NRZ transmission on the one rail, which leads to lower power consumption. We evaluated the proposed RZ/NRZ dual-rail scheme using the ISCAS85 benchmarking circuit. As the results, the proposed circuit shows 25% reduction of the signal transition and the lower power consumption to about 27% than the conventional dual-rail encoding with RZ method, respectively.
Keywords
VLSI; asynchronous circuits; benchmark testing; decoding; pipeline processing; ISCAS85 benchmarking circuit; RZ-NRZ dual-rail decoding scheme; VLSI; asynchronous circuits; asynchronous pipeline; data switching; delay model; dual-rail data encoding; reduced power consumption; signal transition diagram; switching activities reduction; zero switching overhead; Asynchronous circuits; Clocks; Communication switching; Decoding; Delay; Encoding; Energy consumption; Optical signal processing; Pipelines; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Print_ISBN
0-7803-8637-X
Type
conf
DOI
10.1109/APASIC.2004.1349468
Filename
1349468
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