Power efficient scan testing by exploiting existing error tolerance circuitry in a design

Timing errors are a major threat in modern integrated circuits. Suitable error tolerance design techniques exist, like Razor, aiming to confront with this situation. However, the silicon area cost of these solutions makes them unattractive for widespread use. In this paper, aiming to broaden the applicability of timing error tolerance techniques, we explore the ability to extend their use for low power scan testing operations. A low power scan version of the Razor technique is presented, which drastically reduces the scan power consumption by eliminating the signal transitions at the input of the combinational logic during the scan operations.