Modelling Of The Internal Initiation Of Latch-Up In CMOS-VLSI Circuits.

The internal initiation of latch-up in a CMOS circuit is given a quantitative theoritical treatment that leads to a physical model which is favorably compared to the results of the corresponding SPICE simulations. Such an analytical model helps the designer to understand which situation should be expected to be most prone to latch-up in a given circuit. In the light of this analysis, the design of a practical circuit is analysed and internal initiation of latch-up is shown to be the main concern and then the guideline to properly size the transistor´s dimensions of this circuit.