Development of 3 dimensional visualization of semiconductor testing

Wafer test is becoming ever more important to semiconductor designers and manufacturers, due to the ever-increasing cost of test as a proportion of device cost. Hence the knowledge of test concepts and techniques relating to the testing of semiconductor devices is important in the aspect of product development and enhancement. This paper reports on three-dimensional graphic simulation used to explain principles in semiconductor test. The objective is to use computer aided design and animated simulation to provide a visual aid for understanding important qualitative concepts and the underlying formula.