Effect of shallow trench isolation induced stress on CMOS transistor mismatch

Mechanical compressive stress induced by shallow trench isolation (STI) and transistor mismatch is the two important effects that we should take into account when scaling down CMOS transistors. In this paper, we study the relationship between these two effects. Our finding shows that STI induced stress effect improve NMOS Id matching but degrade PMOS Id matching. These effects become more obvious for small size transistors. The STI stress effect has no significant effect on V_t mismatch.