Design of a low power CVSL full adder using low-swing technique

In this paper, we propose a new low-swing CVSL full adder. The circuit provides lower power consumption than previous implementations. We describe an 8 8 parallel multiplier based on this technique. Simulation results comparing the proposed circuit to the previous implementations show its superiority. Power consumption reduction of 13.1% and power-delay-product reduction of 14.2% are achieved. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.35μm standard CMOS process.