• DocumentCode
    1703247
  • Title

    A 10mW 9.7ENOB 80MSPS pipeline ADC in 65nm CMOS process without any special mask requirement and with single 1.3V supply

  • Author

    Das, Abhijit Kumar ; Bhasin, Hemant ; Giduturi, Sundara Siva Rao

  • Author_Institution
    Texas Instrum. India, Bangalore, India
  • fYear
    2009
  • Firstpage
    165
  • Lastpage
    168
  • Abstract
    This paper describes a power and area efficient pipeline ADC design. This ADC was designed in 65 nm process without any special mask requirement and can work with supply voltage of 1.3 V consuming 10 mW providing 9.7 ENOB at 80 MSPS while occupying less than 0.2 square millimeters.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; integrated circuit design; CMOS process; area efficient; pipeline ADC design; power 10 mW; power efficient; size 65 nm; supply voltage; voltage 1.3 V; CMOS process; Pipelines; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-4071-9
  • Electronic_ISBN
    978-1-4244-4073-3
  • Type

    conf

  • DOI
    10.1109/CICC.2009.5280869
  • Filename
    5280869
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1703247