Energy-performance tunable logic

An externally static, internally dynamic topology creates a new logic family that enables the user to tune effective transistor thresholds post-fabrication by adjusting a few power supplies. These gates can therefore be programmed for higher speed or for lower power based on the system requirements. An application of this logic to programmable interconnect circuits is shown in this paper. In a 90-nm test chip, the circuit achieves the same performance as conventional static circuits at 65% energy and has a 2X wider energy-performance tuning range. This property enables building in-field energy-performance tunable FPGAs.