Implementing a digitally synthesized adaptive pre-emphasis algorithm for use in a high-speed backplane interconnection

This paper presents a novel implementation technique using simple digital ASIC synthesis to generate a silicon layout of a multi-level PAM modulation circuit that incorporates a digitally adaptive pre-emphasis scheme. While computationally complex, the actual VLSI implementation is relatively simple, requires minimal power and generates a layout that minimizes the footprint. The results of the digital synthesis of several comparable adaptive circuits are detailed and compared. Several devices have been submitted for fabrication, via CMC, using the TSMC 0.18 μm CMOS generic standard cell process.