• DocumentCode
    1703989
  • Title

    Jaguar: A next-generation low-power x86-64 core

  • Author

    Singh, Taranveer ; Bell, Jonathan ; Southard, S.

  • Author_Institution
    AMD, Austin, TX, USA
  • fYear
    2013
  • Firstpage
    52
  • Lastpage
    53
  • Abstract
    “Jaguar” (JG) is the codename for AMD´s follow-on project to the low-power x86-64 core, codenamed “Bobcat” (BT). AMD´s first 28nm × 86 processor, the 3.08mm2 JG core is designed to support a wide range of applications from low-power tablets requiring sub-5W SoCs to client products up to 25W. Similar to BT, the JG core uses integrated power gating to provide a low-power state for SOC power optimization. A JG compute unit (CU) is constructed using 4 JG cores, four 0.5MB L2 cache modules and an L2 interface (Fig. 3.4.1). An initial SOC has one 26.2mm2 CU, but AMD´s modular design approach allows for different SOC configurations.
  • Keywords
    cache storage; low-power electronics; system-on-chip; AMD follow-on project; AMD modular design approach; Bobcat; CU; JG compute unit; JG core; Jaguar; L2 cache modules; L2 interface; SoC power optimization; integrated power gating; low-power tablets; next-generation low-power x86-64 core; storage capacity 0.5 Mbit; Clocks; Delays; Logic gates; Random access memory; Silicon; Standards; System-on-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4673-4515-6
  • Type

    conf

  • DOI
    10.1109/ISSCC.2013.6487633
  • Filename
    6487633