Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test

A novel Switched Resonant Clocking (SRC) scheme is proposed to solve two basic problems of the conventional resonant clocking, that is, power increase and clock waveform inability at the lower clock frequency region. The power increase prohibits widely-used dynamic frequency scaling (DFS) and the waveform instability hinders low-speed function tests. A test chip in 0.18 mum CMOS is manufactured and measured to show that the SRC suppresses power increase at low clock frequency and enables the low-speed tests, while reducing the clock power by 8% at 1.5-GHz clock with an area penalty of 4.8%.