A multilayer gridless area router for yield improvement

A new multilayer gridless area router to improve the yield of IC layout is presented. The improvement of yield is achieved by reducing the critical areas where circuit faults are likely to happen. This gridless area router utilizes a cost function for critical area computation and heuristically lays the patterns on the places where it is less possible to induce critical areas. The router also takes other objectives into consideration, such as routing completion rate and net length. It takes advantage of gridless routing to gain more flexibility and higher completion rate. The results show that the critical area is effectively decreased by 13% on average while maintaining the routing completion rate over 99%.