An SOC platform for ADC test and measurement

Author

Mullane, Brendan ; Brien, Vincent O. ; MacNamee, Ciaran ; Fleischmann, Thomas

Author_Institution

Dept. of Electron. & Comput. Eng., Univ. of Limerick, Limerick

fYear

2009

Firstpage

4

Lastpage

7

Abstract

An Analog to Digital Converter Built-in-Self-Test design for System-on-Chip applications is presented. Linear and dynamic ADC test occur in parallel to reduce overall test time. A ramp generator is used for linear histogram measurements and a sine-wave signal is applied for dynamic tests. The design precisely measures Hits-per-Code enabling accurate linearity test and a low-area optimal CPU operates dynamic measurements. Results demonstrate efficient silicon area overheads and lower test time capability.

Keywords

analogue-digital conversion; built-in self test; dynamic testing; integrated circuit testing; ramp generators; system-on-chip; analog to digital converter built-in-self-test design; dynamic ADC test; hits-per-code measurement; linear ADC test; linear histogram measurement; low-area optimal CPU; ramp generator; sine-wave signal; system-on-chip applications; Built-in self-test; Circuit testing; Digital signal processing; Electronic equipment testing; Histograms; Integrated circuit testing; Linearity; Signal to noise ratio; System testing; System-on-a-chip; ADC Testing; BIST; DFT; Dynamic Test; Linearity Test; System-on-Chip; component;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits & Systems, 2009. DDECS '09. 12th International Symposium on

Conference_Location

Liberec

Print_ISBN

978-1-4244-3341-4

Electronic_ISBN

978-1-4244-3340-7

Type

conf

DOI

10.1109/DDECS.2009.5012087

Filename

5012087